Architectures for adaptive weight calculation on ASIC and FPGA

R.L. Walke, R.W.M. Smith, G Lightbody

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

30 Citations (Scopus)
52 Downloads (Pure)

Abstract

We compare two parallel urray architectures for adaptive weight calculation based on QR-decomposition by Givens Rotations. We present FPGA implementations of borh orchitectures und compare them with un ASIC-bused solution. The throughput of the FPGA implementations is of the order 5-20 GigaFLOPS, making FPGA a viable alternative to ASIC implementation in applications where power consumption and volume cost ure not critical.
Original languageEnglish
Title of host publicationUnknown Host Publication
Place of PublicationOnline
PublisherIEEE
Pages1375-1380
Number of pages6
ISBN (Print)0-7803-5700-0
DOIs
Publication statusPublished - 6 Aug 2002
EventConference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999. - Pacific Grove, CA, USA , USA
Duration: 6 Aug 2002 → …

Conference

ConferenceConference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers, 1999.
Period6/08/02 → …

Bibliographical note

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[4] C. M. Rader, “VLSI Systolic Arrays for Adaptive Nulling”, IEEE Sig. Proc. Mag, Vol. 13, No. 4, pp. 29-49, 1996.
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[6] G. Lightbody, R. L. Walke, R. Woods, J. McCanny, “Novel Mapping of a Linear QR Architecture”, Proc. ICASSP, vol. IV, pp.
[7] R. Dohler, “Squared Givens Rotations”, IMA J. of NumericalAnalysis, Vol. Il,pp. 1-5, 1991.
[8] S. Y. Kung, VLSIArruy Processors, Prentice Hall, ISBN 0-13-942749-X, 1988.
[9] G. M. Megson, An Introduction to Systolic Algorithm Design, Clarendon Press, ISBN 0-19-853813-8, 1992.

Keywords

  • QR-RLS
  • VLSI
  • VHDL
  • CORDIC
  • systolic arrays

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