Recent studies have shown that the electronic hardware devices can be compromised by the faults and fault tolerance is a crucial capability. This paper addresses the challenge of fault detection in the CMOS circuits, using two bio-inspired structures based on the HP lab's memristor and the BSIM3v3.2.2 transistor models. The first fault detection circuit (FDC) includes the memristor-based synapses and a modified leaky integrate-and-fire (LIF)-based neuron. The memristor-based synapse circuits can be further optimized which is the proposed second fault detection method (O-FDC), and it has a lower hardware overhead and power consumption compared to the former. Experimental results demonstrate that the proposed structures can detect the circuit faults under the inputs of direct current (DC), alternating current (AC) voltage sources, and pulse signals. Under the input of DC, the fault detection times for the two proposed structures are about 0.16 ms and 1.2 ms, respectively; when the input source is AC, the corresponding fault detection times are about 0.206 ms and 0.758 ms; and it takes only 6.47us for fault detection under the input of pulse signals. This work provides an alternative solution to enhance the fault-tolerant capability of the hardware systems.
Bibliographical noteTitle Neurocomputing
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- Fault detection
- Memristive synapses
- Spiking neuron model