Linear QR Architecture for a Single Chip Adaptive Beamformer

G Lightbody, R Walke, R Woods, J McCanny

Research output: Contribution to journalArticlepeer-review

23 Citations (Scopus)

Abstract

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.
Original languageEnglish
Pages (from-to)67-81
JournalThe Journal of VLSI Signal Processing
Volume24
Issue number1
DOIs
Publication statusPublished - 2000

Bibliographical note

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Keywords

  • VLSI
  • systolic arrays
  • QR
  • RLS
  • mapping

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