Rapid design of a single chip adaptive beamformer

G Lightbody, R. Woods, J. McCanny, R. Walke, Y. Hu, D. Trainor

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This paper presents the design of a single chip adaptive beamformer which contains 5 million transistors and can perform 50 GigaFlops. The core processor of the adaptive beamformer is a QR-array processor implemented on a fully efficient linear systolic architecture. The paper highlights a number of rapid design techniques that have been used to realise the design. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of alibrary of parameterisable silicon intellectual property (IP) cores, to rapidly develop the circuit layouts.
Original languageEnglish
Title of host publicationUnknown Host Publication
Place of PublicationOnline
Number of pages10
ISBN (Print)0-7803-4997-0
Publication statusPublished - 6 Aug 2002
EventSignal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on - Cambridge, MA , USA
Duration: 6 Aug 2002 → …


WorkshopSignal Processing Systems, 1998. SIPS 98. 1998 IEEE Workshop on
Period6/08/02 → …

Bibliographical note

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  • QR
  • RLS
  • Systolic array
  • VLSI


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